In the future, the miniaturization of components in integrated circuits will necessitate the production of structures with dimensions that are far below 1 .mu.m. The masks used in the processes previously employed for the production of such submicrometer structures were fabricated by direct write electron or ion beam lithography. Such processes allowed the fabrication of lithographic masks with a field of, say, 5.times.5 mm (size of a chip field) and minimum line widths of about 0.5 .mu.m.
As in the future much larger chip fields with still finer structures will be produced, the larger masks required for this purpose will have to be fabricated with matching accuracy. However, for direct write electron beam exposure systems the writable field size is limited by field inhomogeneities and by the desired finer line widths, since at a constant number of address points, the spacing of the latter and thus the writable field decreases for smaller line widths. Therefore, larger fields can only be produced by successively writing several smaller fields and stitching them together to form a larger field. For this purpose, the individual fields must adjoin each other with maximum accuracy to avoid that positioning errors occurring during field stitching exceed about 1/3 of the minimum line width. On the whole, the fabrication of masks for future highly integrated circuits will lead to an increasing number of positioning errors owing to the finer structures, the resultant smaller writable field, the desired larger mask field, and the larger number of joints per mask (chip) field, respectively, so that it is doubtful whether it will be possible to fabricate masks for future lithography on a 1:1 scale.
Processes for producing structures with dimensions in the submicrometer range by using structures of polymer material with vertical sidewalls are described in the European Patent 0 111 086 (EPA 83109945.2). These processes differ from the present invention taught below.